Digital temperature compensation filtering

ABSTRACT

Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

BACKGROUND

The present technology relates to non-volatile memory systems.

Semiconductor memory devices have become more popular for use in various electronic devices. In a semiconductor memory device, a charge-storing material such as a conductive floating gate or a non-conductive charge-trapping material can be used to store a charge which represents a data state. The memory cell may be a transistor in which the charge-storing material may reside between a channel and a control gate. The charge-storing material may be insulated from both the channel and the control gate. The charge-storing material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers.

Some types of memory cells may be programmed by altering the charge in the charge-storing material, thereby altering the threshold voltage (Vth) of the memory cell transistor. In one technique, a program voltage is applied to the control gate with a low voltage in the channel to add charge to the charge-storing material. After applying the program voltage, the memory cell's threshold voltage is tested by applying a verify voltage to the control gate, and testing whether the memory cell conducts a significant current. Additional program voltages may be applied to control gate, followed by verify voltages, until the memory cell's threshold current is within a target range.

Other types of memory cells can be programmed to different resistance levels. For example, resistive random-access memory (ReRAM) can be reversibly switched between a high resistance state and a low resistance data state. In some memory cells, a ReRAM cell can be reversibly switched between more than two different resistance states. Each resistance state can correspond to a range of resistances.

A memory cell may be read by applying one or more read reference signals to it to determine what range its threshold voltage, resistance, or other physical property falls within. Often, memory cells are programmed in a basic unit referred to as a “page.” The page contains user data and overhead data, in some techniques. Overhead data typically includes parity bits of an Error Correction Code (ECC) that have been calculated from the user data. An error correction controller (ECC) engine encodes user data by adding the parity bits to form a codeword. The ECC engine decodes and error corrects the codeword read from the non-volatile memory system.

The temperature of memory cells can have an effect on the magnitude of the reference signals used to read the state of the cell or

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the different figures.

FIG. 1 is a block diagram depicting one embodiment of a storage system.

FIG. 2A is a block diagram of one embodiment of a memory die.

FIG. 2B is a block diagram of one embodiment of an integrated memory assembly.

FIGS. 2C and 2D depict different embodiments of integrated memory assemblies.

FIG. 3 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

FIG. 4A is a block diagram of a memory structure having two planes.

FIG. 4B depicts a top view of a portion of a block of memory cells.

FIG. 4C depicts a cross sectional view of a portion of a block of memory cells.

FIG. 4D is a cross sectional view of a vertical column of memory cells.

FIG. 4E is a schematic of a plurality of NAND strings showing multiple sub-blocks.

FIG. 5 depicts threshold voltage distributions.

FIG. 6 is a table describing one example of an assignment of data values to data states.

FIG. 7 is a flow chart describing one embodiment of a process for programming non-volatile memory.

FIG. 8 depicts an example of a temperature-sensing circuit, which may be used in the memory system of FIG. 1A.

FIG. 9 is a schematic diagram of a circuit for a sense amplifier.

FIG. 10A is a graph of the temperature compensation value (TEMPCODE) relative to the source voltage for a memory cell.

FIG. 10B is a graph illustrating temperature compensation for various parameters applied to a memory cell relative to changing temperature.

FIG. 11 is a flowchart depicting a method in accordance with the present technology for filtering temperature compensation values.

FIG. 12A illustrates a steady temperature change ramp over time.

FIG. 12B illustrates the effectiveness of each of the hysteresis-inducing function and the digital filtering functions as compared to a prior art temperature compensation design when the memory system is subject to a continuously ramped temperature profile.

FIG. 12C illustrates the effectiveness of a smoothing function relative to a steady temperature change ramp.

FIG. 13A illustrates a stable temperature with noise introduced into the sensed temperature.

FIG. 13B illustrates the effectiveness of each of a prior art temperature compensation design, the hysteresis-inducing function and the digital filtering function when subjected to a stable temperature profile with noise.

FIG. 13C illustrates the effectiveness of a smoothing function relative to a steady temperature with noise in the temperature detection.

FIG. 14A illustrates an ambient temperature profile with large discrete jumps.

FIG. 14B illustrates the effectiveness of each of a prior art temperature compensation design, the hysteresis-inducing function and the digital filtering function described above when the memory system is subjected to a temperature profile which has relatively large magnitude temperature changes.

FIG. 14C illustrates the effectiveness of a smoothing function combining a hysteresis-inducing function and a digital filtering function relative to a temperature profile with large magnitude temperature changes.

DETAILED DESCRIPTION

The present technology pertains to operating non-volatile memory systems. Technology disclosed herein copes with cross-temperature effects in non-volatile memory systems.

Many types of non-volatile memory cells exhibit temperature dependent effects with respect to their data state. For example, some memory cells are programmed by storing charge in either a floating gate or charge trapping region. Typically, the threshold voltage (Vth) of such a memory cell varies with temperature. Thus, if a memory cell is programmed to a certain charge level at one temperature and read at a different temperature, even if the memory cell retains the programmed charge level the threshold voltage may be different. As such, many non-volatile memory systems compensate for temperature by storing temperature values which may be used to change read, verify, program, and erase parameters based on a change in temperature of the system.

Examples are described herein of temperature effects (and technological solutions to compensate for temperature effects) in memory cells which store charge to control the threshold voltage of the memory cell. However, temperature effects (and technological solutions disclosed herein) are not limited to memory cells that store charge to control the threshold voltage. For example, non-volatile memory cells for which a data state is represented by resistance may also exhibit cross-temperature effects. Furthermore, non-volatile memory cells for which a data state is represented by a physical property other than threshold voltage or resistance may also exhibit cross-temperature effects.

The optimum read levels for reading a page of data may depend on temperature. Note that the optimum read levels may depend not only on the present temperature, but also on the program temperature. If the memory system does not compensate for a large temperature change, the bit error rate (BER) may increase. The throughput of the ECC engine may correlate strongly with the BER. For example, the ECC engine may run an algorithm that takes longer to converge when the BER is higher. Thus, large cross-temperatures can decrease memory system performance (e.g., throughput).

Users may observe this as FBC fluctuations during repeated reads. There is also a concern that if some operation such as read-level optimization is done at such a critical temperature, the result may be invalid.

FIG. 1 is a block diagram of one embodiment of a storage system 100 that implements the proposed technology described herein. In one embodiment, storage system 100 is a solid-state drive (“SSD”). Storage system 100 can also be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system. Storage system 100 is connected to host 102, which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host 102 is separate from, but connected to, storage system 100. In other embodiments, storage system 100 is embedded within host 102.

The components of storage system 100 depicted in FIG. 1 are electrical circuits. Storage system 100 includes a memory controller 120 connected to non-volatile memory 130 and local high speed volatile memory 140 (e.g., DRAM). Local high speed volatile memory 140 is used by memory controller 120 to perform certain functions. For example, local high speed volatile memory 140 stores logical to physical address translation tables (“L2P tables”).

Memory controller 120 comprises a host interface 152 that is connected to and in communication with host 102. In one embodiment, host interface 152 implements a NVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. NOC's can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOC 154 can be replaced by a bus. Connected to and in communication with NOC 154 is processor 156, ECC engine 158, memory interface 160, and DRAM controller 164. DRAM controller 164 is used to operate and communicate with local high speed volatile memory 140 (e.g., DRAM). In other embodiments, local high speed volatile memory 140 can be SRAM or another type of volatile memory.

ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine 158 is an electrical circuit programmed by software. For example, ECC engine 158 can be a processor that can be programmed. In other embodiments, ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 158 is implemented by processor 156.

Processor 156 performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom and dedicated hardware circuit without any software. Processor 156 also implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To implement this system, memory controller 120 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain tables (i.e. the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memory 140 cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a memory die 130 and a subset of the L2P tables are cached (L2P cache) in the local high speed volatile memory 140.

Memory interface 160 communicates with non-volatile memory 130. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface 160 (or another portion of controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.

In one embodiment, non-volatile memory 130 comprises one or more memory die. FIG. 2A is a functional block diagram of one embodiment of a memory die 200 that comprises non-volatile memory 130. Each of the one or more memory die of non-volatile memory 130 can be implemented as memory die 200 of FIG. 2A. The components depicted in FIG. 2A are electrical circuits. Memory die 200 includes a memory array 202 that can comprise non-volatile memory cells, as described in more detail below. The array terminal lines of memory array 202 include the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented. Memory die 200 includes row control circuitry 220, whose outputs 208 are connected to respective word lines of the memory array 202. Row control circuitry 220 receives a group of M row address signals and one or more various control signals from System Control Logic circuit 206, and typically may include such circuits as row decoders 222, array terminal drivers 224, and block select circuitry 226 for both reading and writing (programming) operations. Row control circuitry 220 may also include read/write circuitry. Memory die 200 also includes column control circuitry 210 including sense amplifier(s) 230 whose input/outputs 206 are connected to respective bit lines of the memory array 202. Although only single block is shown for array 202, a memory die can include multiple arrays that can be individually accessed. Column control circuitry 210 receives a group of N column address signals and one or more various control signals from System Control Logic 260, and typically may include such circuits as column decoders 212, array terminal receivers or driver circuits 214, block select circuitry 216, as well as read/write circuitry, and I/O multiplexers.

System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which comprises one or more electrical circuits) include state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 262 is replaced by a micro-controller or microprocessor, either on or off the memory chip. System control logic 262 can also include a power control module 264 that controls the power and voltages supplied to the rows and columns of the memory structure 202 during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic 262 includes storage 366 (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory array 202.

Commands and data are transferred between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as a “communication interface”). Memory controller interface 268 is an electrical interface for communicating with memory controller 120. Examples of memory controller interface 268 include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used.

In some embodiments, all the elements of memory die 200, including the system control logic 360, can be formed as part of a single die. In other embodiments, some or all of the system control logic 260 can be formed on a different die.

In one embodiment, memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers.

In another embodiment, memory structure 302 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memories (resistive random-access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below.

Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb₂Te₃ super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate.

A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

The elements of FIG. 2A can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuitry, which includes all of the other components depicted in FIG. 2A. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of storage system 100 that is given over to the memory structure 202; however, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic 260, reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the storage system 100 is the amount of area to devote to the memory structure 202 and the amount of area to devote to the peripheral circuitry.

Another area in which the memory structure 202 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 202 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies.

To improve upon these limitations, embodiments described below can separate the elements of FIG. 2A onto separately formed dies that are then bonded together. More specifically, the memory structure 302 can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more die, such as two memory die and one control die, for example.

FIG. 2B shows an alternative arrangement to that of FIG. 2A which may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B depicts a functional block diagram of one embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 may be used to implement the non-volatile memory 130 of storage system 100. The integrated memory assembly 307 includes two types of semiconductor die (or more succinctly, “die”). Memory die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

FIG. 2B shows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die 311 coupled to memory structure 202 formed in memory die 201. Common components are labelled similarly to FIG. 2A. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of the column control circuitry 210 and all or a portion of the row control circuitry 220 are located on the memory die 201. In some embodiments, some of the circuitry in the system control logic 260 is located on the on the memory die 201.

System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while moving such circuits from a die such as memory 2 die 201 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 311 may not require many additional process steps. The control die 211 could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 260, 210, 220.

FIG. 2B shows column control circuitry 210 including sense amplifier(s) 230 on the control die 211 coupled to memory structure 202 on the memory die 201 through electrical paths 206. For example, electrical paths 206 may provide electrical connection between column decoder 212, driver circuitry 214, and block select 216 and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of the memory die 201, which are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical paths 306, including a pair of bond pads, which connects to column control circuitry 210. Similarly, row control circuitry 220, including row decoder 222, array drivers 224, and block select 226 are coupled to memory structure 202 through electrical paths 208. Each of electrical path 208 may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die 211 and memory die 201.

For purposes of this document, the phrase “one or more control circuits” can include any one of or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row contrail circuitry 200, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and/or other similar functioned circuits. The one or more control circuits can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

In some embodiments, there is more than one control die 211 and more than one memory die 201 in an integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control die 211 and multiple memory die 201. FIG. 2C depicts a side view of an embodiment of an integrated memory assembly 207 stacked on a substrate 271 (e.g., a stack comprising control dies 211 and memory dies 201). The integrated memory assembly 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201and more than three control die 211.

Each control die 211 is affixed (e.g., bonded) to at least one of the memory dies 201. Some of the bond pads 282/284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. This solid layer 280 protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as solid layer 280, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

The integrated memory assembly 207 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. A number of such wire bonds may be formed across the width of each control die 211 (i.e., into the page of FIG. 2C).

A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211. The TSVs 276, 278 may be formed before, during or after formation of the integrated circuits in the semiconductor dies 201, 211. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package. The solder balls 272 may form a part of the interface between integrated memory assembly 207 and memory controller 120.

FIG. 2D depicts a side view of another embodiment of an integrated memory assembly 207 stacked on a substrate 271. The integrated memory assembly 206 of FIG. 2D has three control die 211 and three memory die 201. In some embodiments, there are many more than three memory dies 201 and many more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 may be bonded to two or more memory die 201.

Some of the bond pads 282, 284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. In contrast to the example in FIG. 2C, the integrated memory assembly 207 in FIG. 2D does not have a stepped offset. A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package.

As has been briefly discussed above, the control die 211 and the memory die 201 may be bonded together. Bond pads on each die 201, 211 may be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu.

When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller sizes and pitches.

Some embodiments may include a film on surface of the dies 201, 211. Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

FIG. 3 is a perspective view of a portion of one example embodiment of a monolithic three-dimensional memory array/structure that can comprise memory structure 202, which includes a plurality non-volatile memory cells arranged as vertical NAND strings. For example, FIG. 3 shows a portion of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-300 alternating dielectric layers and conductive layers. More or less than 108-300 layers can also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four or more regions (e.g., sub-blocks) by local interconnects LI. FIG. 3 shows two fingers and two local interconnects LI. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 3 , the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three-dimensional monolithic memory array that comprises memory structure 202 is provided below with respect to FIG. 4A-4E.

FIG. 4A is a block diagram explaining one example organization of memory structure 326, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In on embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize the memory structure 326 to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells as the memory cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block. Although FIG. 4A shows two planes 302/304, more or less than two planes can be implemented. Ion some embodiments, memory structure 202 includes four planes.

FIGS. 4B-4E depict an example three dimensional (“3D”) NAND structure that corresponds to the structure of FIG. 3 and can be used to implement memory structure 202 of FIGS. 2A and 2B. FIG. 4B is a block diagram depicting a top view of a portion of one block from memory structure 326. The portion of the block depicted in FIG. 4B corresponds to portion 306 in block 2 of FIG. 4A. As can be seen from FIG. 4B, the block depicted in FIG. 4B extends in the direction of 332. In one embodiment, the memory array has many layers; however, FIG. 4B only shows the top layer.

FIG. 4B depicts a plurality of circles that represent the vertical columns. Each of the vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example, FIG. 4B depicts vertical columns 422, 432, 442 and 452. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details of the vertical columns are provided below. Since the block depicted in FIG. 4B extends in the direction of arrow 332, the block includes more vertical columns than depicted in FIG. 4B

FIG. 4B also depicts a set of bit lines 415, including bit lines 411, 412, 413, 414, . . . 419. FIG. 4B shows twenty-four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty-four bit lines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442 and 452.

The block depicted in FIG. 4B includes a set of local interconnects 402, 404, 406, 408 and 410 that connect the various layers to a source line below the vertical columns. Local interconnects 402, 404, 406, 408 and 410 also serve to divide each layer of the block into four regions; for example, the top layer depicted in FIG. 4B is divided into regions 420, 430, 440 and 450, which are referred to as fingers. In the layers of the block that implement memory cells, the four regions are referred to as word line fingers that are separated by the local interconnects. In one embodiment, the word line fingers on a common level of a block connect together to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In one example implementation, a bit line only connects to one vertical column in each of regions 420, 430, 440 and 450. In that implementation, each block has sixteen rows of active columns and each bit line connects to four rows in each block. In one embodiment, all of four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together); therefore, the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).

Although FIG. 4B shows each region having four rows of vertical columns, four regions and sixteen rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block.

FIG. 4B also shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

FIG. 4C depicts a portion of one embodiment of a three-dimensional memory structure 326 showing a cross-sectional view along line AA of FIG. 4B. This cross-sectional view cuts through vertical columns 432 and 434 and region 430 (see FIG. 4B). The structure of FIG. 4C includes four drain side select layers SGD0, SGD1, SGD2 and SGD3; four source side select layers SGS0, SGS1, SGS2 and SGS3; six dummy word line layers DD0, DD1, DS0, DS1, WLDL, WLDU; and ninety-six data word line layers WLL0-WLL95 for connecting to data memory cells. Other embodiments can implement more or less than four drain side select layers, more or less than four source side select layers, more or less than six dummy word line layers, and more or less than ninety six word lines. Vertical columns 432 and 434 are depicted protruding through the drain side select layers, source side select layers, dummy word line layers and word line layers. In one embodiment, each vertical column comprises a vertical NAND string. For example, vertical column 432 comprises NAND string 484. Below the vertical columns and the layers listed below is substrate 101, an insulating film 454 on the substrate, and source line SL. The NAND string of vertical column 432 has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with FIG. 4B, FIG. 4C show vertical column 432 connected to Bit Line 414 via connector 417. Local interconnects 404 and 406 are also depicted.

For ease of reference, drain side select layers SGD0, SGD1, SGD2 and SGD3; source side select layers SGS0, SGS1, SGS2 and SGS3; dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU; and data word line layers WLL0-WLL95 collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL0-DL111. For example, dielectric layers DL104 is above word line layer WLL94 and below word line layer WLL95. In one embodiment, the dielectric layers are made from SiO₂. In other embodiments, other dielectric materials can be used to form the dielectric layers.

In one embodiment, drain side select layers SGD0, SGD1, SGD2 and SGD3 drain side selection lines; source side select layers SGS0, SGS1, SGS2 and SGS3 implement source side selection lines; dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU implement dummy word lines; and data word line layers WLL0-WLL95 implement data word lines. In one embodiment, data word lines, dummy word lines, drain side selection lines and source side selection lines are all referred to generically as word lines.

The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WLL0-WLL95 connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. A dummy word line is connected to dummy memory cells. Drain side select layers SGD0, SGD1, SGD2 and SGD3 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, SGS2 and SGS3 are used to electrically connect and disconnect NAND strings from the source line SL.

FIG. 4C also shows a Joint area. In one embodiment it is expensive and/or challenging to etch ninety-six word line layers intermixed with dielectric layers. To ease this burden, one embodiment includes laying down a first stack of forty-eight word line layers alternating with dielectric layers, laying down the Joint area, and laying down a second stack of forty eight word line layers alternating with dielectric layers. The Joint area is positioned between the first stack and the second stack. The Joint area is used to connect to the first stack to the second stack. In FIG. 4C, the first stack is labeled as the “Lower Set of Word Lines” and the second stack is labeled as the “Upper Set of Word Lines.” In one embodiment, the Joint area is made from the same materials as the word line layers. In one example set of implementations, the plurality of word lines (word lines are one example of control lines, bit lines can also be considered control lines) comprises a first stack of alternating word line layers and dielectric layers, a second stack of alternating word line layers and dielectric layers, and a joint area between the first stack and the second stack, as depicted in FIG. 4C.

FIG. 4D depicts a cross sectional view of region 429 of FIG. 4C that includes a portion of vertical column 432 (a memory hole). In one embodiment, the vertical columns are round; however, in other embodiments other shapes can be used. In one embodiment, vertical column 432 includes an inner core layer 470 that is made of a dielectric, such as SiO₂. Other materials can also be used. Surrounding inner core 470 is polysilicon channel 471. Materials other than polysilicon can also be used. Note that it is the channel 471 that connects to the bit line and the source line. Surrounding channel 471 is a tunneling dielectric 472. In one embodiment, tunneling dielectric 472 has an ONO structure. Surrounding tunneling dielectric 472 is charge trapping layer 473, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure.

FIG. 4D depicts dielectric layers DLL105, DLL104, DLL103, DLL102 and DLL101, as well as word line layers WLL95, WLL94, WLL93, WLL92, and WLL91. Each of the word line layers includes a word line region 476 surrounded by an aluminum oxide layer 477, which is surrounded by a blocking oxide layer 478. In other embodiments, the blocking oxide layer can be a vertical layer parallel and adjacent to charge trapping layer 473. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel 471, tunneling dielectric 472, charge trapping layer 473, blocking oxide layer 478, aluminum oxide layer 477 and word line region 476. For example, word line layer WLL95 and a portion of vertical column 432 comprise a memory cell MC1. Word line layer WLL94 and a portion of vertical column 432 comprise a memory cell MC2. Word line layer WLL93 and a portion of vertical column 432 comprise a memory cell MC3. Word line layer WLL92 and a portion of vertical column 432 comprise a memory cell MC4. Word line layer WLL91 and a portion of vertical column 432 comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 473 which is associated with the memory cell. These electrons are drawn into the charge trapping layer 473 from the channel 471, through the tunneling dielectric 472, in response to an appropriate voltage on word line region 476. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL).

FIG. 4E is a schematic diagram of a portion of the memory depicted in in FIGS. 3-4D. FIG. 4E shows physical data word lines WLL0-WLL95 running across the entire block. The structure of FIG. 4E corresponds to portion 306 in Block 2 of FIGS. 4A-D, including bit lines 411, 412, 413, 414, . . . 419. Within the block, each bit line is connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2 and SGD3 are used to determine which of the four NAND strings connect to the associated bit line(s). Source side selection lines SGS0, SGS1, SGS2 and SGS3 are used to determine which of the four NAND strings connect to the common source line. The block can also be thought of as divided into four sub-blocks SB0, SB1, SB2 and SB3. Sub-block SB0 corresponds to those vertical NAND strings controlled by SGD0 and SGS0, sub-block SB1 corresponds to those vertical NAND strings controlled by SGD1 and SGS1, sub-block SB2 corresponds to those vertical NAND strings controlled by SGD2 and SGS2, and sub-block SB3 corresponds to those vertical NAND strings controlled by SGD3 and SGS3.

Although the example memory system of FIGS. 3-4E is a three-dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein.

The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. FIG. 5 is a graph of threshold voltage versus number of memory cells, and illustrates example threshold voltage distributions for the memory array when each memory cell stores three bits of data. Other embodiments, however, may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell). FIG. 5 shows eight threshold voltage distributions, corresponding to eight data states. For a data state N, that data state N has higher threshold voltages than data state N−1 and lower threshold voltages than data state N+1. The first threshold voltage distribution (data state) SO represents memory cells that are erased. The other seven threshold voltage distributions (data states) S1-S7 represent memory cells that are programmed and, therefore, are also called programmed states or programmed data states. In some embodiments, data states S1-S7 can overlap, with controller 122 relying on error correction to identify the correct data being stored.

FIG. 5 shows seven read reference voltages, Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., S0, S1, S2, S3, . . . ) a memory cell is in.

FIG. 5 also shows seven verify reference voltages, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 (also referred to as verify target voltages). When programming memory cells to data state S1, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv1. When programming memory cells to data state S2, the system will test whether the memory cells have threshold voltages greater than or equal to Vv2. When programming memory cells to data state S3, the system will determine whether memory cells have their threshold voltage greater than or equal to Vv3. When programming memory cells to data state S4, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv4. When programming memory cells to data state S5, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv5. When programming memory cells to data state S6, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv6. When programming memory cells to data state S7, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv7.

In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state S0 directly to any of the programmed data states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program memory cells directly into data states S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and/or from data state S0 to data state S3, and so on. The arrows of FIG. 5 represent the full sequence programming. The technology described herein can also be used with other types of programming in addition to full sequence programming including (but not limited to) multiple stage/phase programming.

Each threshold voltage distribution (data state) of FIG. 5 corresponds to predetermined values for the set of data bits stored in the memory cells. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the memory cell depends upon the data encoding scheme adopted for the memory cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected.

FIG. 6 is a table describing one example of an assignment of data values to data states. In the table of FIG. 6 , SO=111 (erased state), S1=110, S2=100, S3=000, S4=010, S5=011, S6=001 and S7=101. Other encodings of data can also be used. No particular data encoding is required by the technology disclosed herein. In one embodiment, when a block is subjected to an erase operation, all memory cells are moved to data state SO, the erased state.

In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of FIG. 5 ) or verify operation (e.g. see verify reference voltages Ev, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 of FIG. 5 ) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.

FIG. 7 is a flowchart describing one embodiment of a process for programming that is performed by memory die 200 and/or integrated assembly 207. In one example embodiment, the process of FIG. 7 is performed on memory die 200 using the control circuitry (system control logic 260, column control circuitry 210, row control circuitry 220) discussed above. In one example embodiment, the process of FIG. 7 is performed by integrated memory assembly 207 using the control circuitry (system control logic 260, column control circuitry 210, row control circuitry 220) of control die 211 to program memory cells on memory die 201. The process includes multiple loops, each of which includes a program phase and a verify phase. The process of FIG. 7 is performed to implement the full sequence programming, as well as other programming schemes including multi-stage programming. When implementing multi-stage programming, the process of FIG. 7 is used to implement any/each stage of the multi-stage programming process.

Typically, the program voltage applied to the control gates (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 502 of FIG. 7 , the program voltage (Vpgm) is initialized to the starting magnitude (e.g., ˜12-20 V or another suitable level) and a program counter PC maintained by state machine 262 is initialized at 1.

In one embodiment, the set of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same data word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step 504 the storage system will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In step 506, NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected data word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes. A program inhibit voltage is applied to the bit lines coupled the unselected NAND string.

In step 508, a program pulse (e.g., voltage pulse) of the program signal Vpgm is applied to the selected word line (the data word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage, in one embodiment. Herein, such a NAND string is referred to as a “selected NAND string.” In step 508, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all the memory cells connected to the selected word line will concurrently have their Vt change, unless they are inhibited from programming.

In step 510, memory cells that have reached their target states are locked out from further programming. Step 510 may include performing verifying at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage.

In step 510, a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state. If, in step 512, it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 514. Otherwise if, in step 512, it is determined that not all the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 516.

In step 516, the system counts the number of memory cells that have not yet reached their respective target Vt distribution. That is, the system counts the number of memory cells that have, so far, failed to reach their target state. This counting can be done by the state machine 262, the memory controller 120, or other logic. In one implementation, each of the sense blocks will store the status (pass/fail) of their respective cells. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.

In step 518, it is determined whether the count from step 516 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for a page (e.g., the unit of programming and the unit of reading) of memory cells. If the number of failed cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step 514. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 518 is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a pro-rata (or other) portion of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.

If the number of failed memory cells is not less than the predetermined limit, than the programming process continues at step 520 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 1, 12, 16, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 524. If the program counter PC is less than the program limit value PL, then the process continues at step 522 during which time the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-1.0 volts). After step 522, the process loops back to step 504 and another program pulse is applied to the selected word line so that another iteration (steps 504-522) of the programming process of FIG. 7 is performed.

Because it is possible that errors can occur when programming or reading, and errors can occur while storing data (e.g., due to electrons drifting, data retention issues or other phenomenon), error correction is used with the programming of data. Memory systems often use Error Correction Codes (ECC) to protect data from corruption. Many ECC coding schemes are well known in the art. These conventional error correction codes are especially useful in large scale memories, including flash (and other non-volatile) memories, because of the substantial impact on manufacturing yield and device reliability that such coding schemes can provide, rendering devices that have a few non-programmable or defective cells as useable. Of course, a tradeoff exists between the yield savings and the cost of providing additional memory cells to store the code bits (i.e., the code “rate”). As such, some ECC codes are better suited for flash memory devices than others. Generally, ECC codes for flash memory devices tend to have higher code rates (i.e., a lower ratio of code bits to data bits) than the codes used in data communications applications (which may have code rates as low as ½). Examples of well-known ECC codes commonly used in connection with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Sometimes, the error correction codes used in connection with flash memory storage are “systematic,” in that the data portion of the eventual code word is unchanged from the actual data being encoded, with the code or parity bits appended to the data bits to form the complete code word.

The particular parameters for a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the overall length of the code word after encoding. For example, a typical BCH code applied to a sector of 512 bytes (4096 bits) of data can correct up to four error bits, if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes, and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512 byte sector of data, using about 72 ECC bits. In the flash memory context, error correction coding provides substantial improvement in manufacturing yield, as well as in the reliability of the flash memory over time.

In some embodiments, memory controller 120 receives host data (also referred to as user data or data from an entity external to the memory system), also referred to as information bits, that is to be stored non-volatile memory structure 202. The informational bits are represented by the matrix i=[1 0] (note that two bits are used for example purposes only, and many embodiments have code words longer than two bits). An error correction coding process (such as any of the processes mentioned above or below) is implemented by ECC engine 158 of memory controller 120 in which parity bits are added to the informational bits to provide data represented by the matrix or code word v=[1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used that map input data to output data in more complex manners. For example, low density parity check (LDPC) codes, also referred to as Gallager codes, can be used. More details about LDPC codes can be found in R.G. Gallager, “Low-density parity-check codes,” IRE Trans. Inform. Theory, vol. IT-8, pp. 21 28, Jan. 1962; and D. MacKay, Information Theory, Inference and Learning Algorithms, Cambridge University Press 2003, chapter 47. In practice, such LDPC codes are typically applied (e.g., by ECC engine 158) to multiple pages encoded across a number of memory cells, but they do not need to be applied across multiple pages. The data bits can be mapped to a logical page and stored in memory structure 202 by programming one or more memory cells to one or more programming states, which corresponds to v.

In one embodiment, programming serves to raise the threshold voltage of the memory cells to one of the programmed data states S1-S7. Erasing serves to lower the threshold voltage of the memory cells to the Erase data state S0.

One technique to erase memory cells in some memory devices is to bias a p-well (or other types of) substrate to a high voltage to charge up a NAND channel. An erase enable voltage (e.g., a low voltage) is applied to control gates of memory cells while the NAND channel is at a high voltage to erase the non-volatile storage elements (memory cells). Herein, this is referred to as p-well erase.

Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the NAND string channel potential to erase the memory cells. Herein, this is referred to as GIDL erase. Both p-well erase and GIDL erase may be used to lower the threshold voltage (Vt) of memory cells.

In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a select transistor (e.g., SGD and/or SGS). A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current may result when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers, e.g., holes, predominantly moving into NAND channel, thereby raising potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel, in the direction of a bit line or in the direction of a source line, by an electric field. During erase, the holes may tunnel from the channel to a charge storage region of memory cells and recombine with electrons there, to lower the threshold voltage of the memory cells.

The GIDL current may be generated at either end of the NAND string. A first GIDL voltage may be created between two terminals of a select transistor (e.g., drain side select transistor) that is connected to a bit line to generate a first GIDL current. A second GIDL voltage may be created between two terminals of a select transistor (e.g., source side select transistor) that is connected to a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of the NAND string is referred to as a one-sided GIDL erase. Erasing based on GIDL current at both ends of the NAND string is referred to as a two-sided GIDL erase.

A non-volatile storage system in disclosed that uses multiple triple wells and groups the word line switch transistors into triple wells based on word line voltage ranges used during the programming process. In one embodiment, for a given block, the word line switch transistors connected to data word lines are positioned in a first triple well and the word line switch transistors connected to selection and dummy word lines are positioned in a second triple well. This structure allows the triple wells to be biased differently such that the voltage difference across the word line switch transistors is reduced. Since the word line switch transistors need only accommodate a smaller voltage differences than prior memory systems, the word line switch transistors can be made smaller, thereby, reducing the area on the semiconductor die used for the word line switch transistors.

As discussed above with respect to FIG. 7 , one embodiment for programming comprises applying a high voltage on a selected data word line, with other voltages on unselected word lines and appropriate voltages on selection lines (e.g., SGD, SGS). The unselected data word lines are those data word lines other than the selected word line. One technique for applying the necessary voltages to the word lines is through word line switch transistors. For some techniques, in order to turn on the word line switch transistor to transfer the program voltage to the word line, the gate of the word line switch transistor needs to be biased to at least the program voltage plus the transistor's threshold voltage. Therefore, in some cases the voltage applied to the gate of the word line switch transistor could be ˜29 volts. In the past, all word line switch transistors are implemented in a common triple well that is typically biased at 0 volts during programming. Therefore, the word line switch transistors will need to be big enough to reliably absorb the stress of 29 volts across the gate to the channel.

The largest voltage across the word line transistor occurs during programming. To reduce the voltage across the word line switch transistors, it one may use multiple triple wells and group the word line switch transistors into triple wells based on word line voltage ranges used during the programming process. In one embodiment, for a given block, the word line switch transistors connected to data word lines are positioned in a first triple well and the word line switch transistors connected to selection and dummy word lines are positioned in a second triple well. This structure allows the triple wells to be biased differently such that the voltage difference across the word line switch transistors is reduced. Since the word line switch transistors need only accommodate smaller voltage differences than prior memory systems, the word line switch transistors can be smaller, thereby, reducing the area on the semiconductor die used for the word line switch transistors.

In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of FIG. 5 ) or verify operation (e.g. see verify target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 of FIG. 5 ) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.

FIG. 8 is a schematic diagram of one example embodiment of a sense amplifier circuit that can be used to measure the conduction current of a memory cell during a read or verify operation, which may comprise sense amplifiers 230 illustrated above. As described below, the circuit of FIG. 8 pre-charges a capacitor (or other charge storage device) to a pre-charge magnitude, discharges the capacitor through the memory cell for the duration of a sense time, and senses voltage at the capacitor after the sense time. The sense voltage will be indicative of whether the memory cells conducted the current being sensed for, which is indicative of whether the threshold voltage of the memory cell is greater than or less than threshold voltage being tested for. If the threshold voltage of the memory cell is greater than the threshold voltage being tested, then, during a verify operation, the memory cell will complete programming, as appropriate based on the processes described herein. FIG. 8 shows transistor 800 connected to the Bit Line and transistor 802. Transistor 800 receives the signal BLS at its gate, and is used to connect to or isolate the Bit Line. Transistor 802 receives the signal BLC at its gate, and is used as a voltage clamp. The gate voltage BLC is biased at a constant voltage equal to the desired Bit Line voltage plus the threshold voltage of transistor 802. The function of transistor 802, therefore, is to maintain a constant Bit Line voltage during a sensing operation (during read or verify), even if the current through the Bit Line changes.

Transistor 802 is connected to transistors 804, 806 and 808. Transistor 806 is connected to capacitor 816 at the node marked SEN. The purpose of transistor 806 is to connect capacitor 816 to Bit Line 800 and disconnect capacitor 816 from Bit Line 800 so that capacitor 816 is in selective communication with Bit Line 800. In other words, transistor 806 regulates the sense time. That is, while transistor 806 is turned on capacitor 816 can discharge through the Bit Line, and when transistor 806 is turned off capacitor 816 cannot discharge through the Bit Line. To control the sense time, the state machine 812 (optionally at the direction of Controller 822) controls transistor 806.

The node at which transistor 806 connects to capacitor 816 is also connected to transistor 810 and transistor 814. Transistor 810 is connected to transistors 808, 812 and 818. Transistor 818 is also connected to transistor 820. Transistors 818 and 820 are PMOS transistors while the other transistors of FIG. 8 are NMOS transistors. Transistors 810, 818, and 820 provide a pre-charging path to capacitor 816. A voltage (e.g. Vdd or other voltage) is applied to the source of transistor 820. By appropriately biasing transistors 810, 818 and 820, the voltage applied to the source of transistor 820 can be used to pre-charge capacitor 816. After pre-charging, capacitor 816 can discharge through the Bit Line via transistor 806 (assuming that transistors 800 and 802 are conducting).

The circuit of FIG. 8 includes inverters 830 and 832 forming a latch circuit. The output of inverter 832 is connected to the input of inverter 830 and the output of inverter 830 is connected to the input of inverter 832. as well as transistors 820 and 822. The input of inverter 832 will receive Vdd and the two inverters 830, 832 will act as a latch to store Vdd. The input of inverter 832 can also be connected to another value. Transistors 812 and 822 provide a path for communicating the data stored by inverters 830 and 832 to transistor 814. Transistor 822 receives the signal FCO at its gate. Transistor 812 receives the signal STRO at its gate. By raising or lowering FCO and STRO, a path is provided or cut off between the inverters 830, 832 and transistor (sensing switch) 814. The gate of transistor 814 is connected capacitor 816, transistor 806 and transistor 810 at the node marked SEN. The other end of capacitor 816 is connected to the signal CLK.

As discussed above, capacitor 816 is pre-charged via transistors 810, 818 and 820. This will raise the voltage at the SEN node to a pre-charge voltage level (Vpre). When transistor 806 turns on, capacitor 816 can discharge its charge through the Bit Line and the selected memory cell if the threshold voltage of the memory cell is below the voltage level being tested for. If the capacitor 816 is able to discharge, then the voltage at the capacitor (at the SEN node) will decrease.

The pre-charge voltage (Vpre) at the SEN node is greater than the threshold voltage of transistor 814; therefore, prior to the sense time, transistor 814 is on (conducting). Since transistor 814 is on during the sense time, then transistor 812 should be off. If the capacitor does not discharge during the sense time, then the voltage at the SEN node will remain above the threshold voltage of transistor 814 and the charge at the inverters 830, 832 can be discharged into the CLK signal when STRO turns on transistor 812. If the capacitor discharges sufficiently during the sense time, then the voltage at the SEN node will decrease below the threshold voltage of transistor 814; thereby, turning off transistor 914 and the data (e.g., Vdd) stored at inverters 830, 832 from being discharged through CLK. So testing whether the diodes 830, 832 maintain their charge or discharge will indicate the result of the verification process. In one embodiment, the result can be read at node A via transistor 834 (Data Out) by turning on transistor 834 gate signal NCO.

The pre-charge level of capacitor 816 (and, thus, the pre-charge voltage at node SEN) is limited by the current passing through transistor 810. The current that passes through transistor 810 is limited by the gate voltage H00. As such, the pre-charge voltage at node SEN is limited by the voltage H00 less the threshold voltage of transistor 810. With this arrangement, the system can regulate the pre-charge voltage at node SEN by regulating H00. A larger voltage at H00 results in a larger voltage at the SEN node when pre-charging. A lower voltage at H00 results in a lower voltage at the SEN node when pre-charging.

When the system performs a read or verify operation (both are sense operations), the voltage applied to the control gate of the cell may cause the channel (connected to the bit line) of the cell to conduct. If this happens, a capacitor is discharged through the channel, lowering in voltage as it discharges.

In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of FIG. 5 ) or verify operation (e.g. see verify target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7of FIG. 5 ) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.

FIG. 9 depicts an example of a temperature-sensing circuit 915, which may be used in the memory system 100 of FIG. 1 . In this example, the temperature-sensing circuit 915 stores a temperature code in storage region 913. The circuit includes pMOSFETs 931 a, 931 b and 934, bipolar transistors 933 a and 933 b and resistors R1, R2 and R3. I1, I2 and I3 denote currents. Voutput is a temperature-based output voltage provided to an analog-to-digital (ADC) converter 929. Vbg is a temperature-independent voltage. A voltage level generation circuit 935 uses Vbg to set a number of voltage levels. For example, a reference voltage may be divided down into several levels by a resistor divider circuit.

The ADC compares Voutput to the voltage levels and selects a closest match among the voltage levels, outputting a corresponding digital value (VTemp) to the storage region 913. This is data indicating a temperature of the memory device.

Vbg, is obtained by adding the base-emitter voltage (Vbe) across the transistor 931 b and the voltage drop across the resistor R2. The bipolar transistor 933 a has a larger area (by a factor N) than the transistor 933 b. The PMOS transistors 931 a and 931 b are equal in size and are arranged in a current mirror configuration so that the currents I1 and I2 are substantially equal. We have Vbg=Vbe+R2×I2 and I1=Ve/R1 so that I2=Ve/R1. As a result, Vbg=Vbe+R2×kT ln(N)/R1xq, where T is temperature, k is Boltzmann's constant and q is a unit of electric charge. The source of the transistor 934 is connected to a supply voltage Vdd and the node between the transistor's drain and the resistor R3 is the output voltage, Voutput. The gate of the transistor 934 is connected to the same terminal as the gates of transistors 931 a and 931 b and the current through the transistor 934 mirrors the current through the transistors 931 a and 931 b.

The VTemp value stored in storage region 912 is a digital value referred to herein as a digital temperature code or “TEMPCODE”. The TEMPCODE is a binary string, in one embodiment. One or more TEMPCODE values may be retained in the storage region. When a read, verify, program, or erase operation is to be performed, a sensed temperature prior to the read/verify/program/erase operation may comprise the system's “current temperature value”, while previously applied TEMPCODE values comprise “historical temperature values.”

To accommodate temperature-dependent variations in memory cells, temperature compensation can occur during read and verify sensing, such as for example, at the beginning of any read or program verify operation. Temperature compensation may also occur to adjust parameters used for program or erase operations. In embodiments, the temperature is determined and various operating parameters can be adjusted, such as the cell's source voltage (V_(CESRC)−applied to the source line SL (shown in FIG. 4E)), a cell's bit line (BL) voltage (VBL), a cell's control gate voltage (V_(CG), where V_(CGRV) is the control gate read/verify voltage), the length of the sense time, the sense current, and any other read/verify/program/erase parameter.

In prior art designs, each read/verify/program/erase parameter may be compensated for based on a change between successive temperature measurements during successive read/verify/program/erase operations. Any number of parameters used in such operations may be modified (adjusted higher or lower, or longer or shorter), in order to compensate for variations in temperature between successive operations.

In various embodiments, the memory system 100 utilizes “digital” temperature compensation where temperature compensation is based on the TEMPCODE value. Digital calculations are made to determine what quantized voltage level or time duration should be used for various parameters. In some embodiments, the voltage level resolution is relatively large. In addition, each parameter may be adjusted at one or more different temperature changes, but in certain instances, the temperature compensation change point for various parameters may converge, resulting in multiple parameters changing at the same time. In some cases, a number of degrees (Celsius) of temperature change are required to result in a parameter's target voltage to be increased or decreased. Part of the reason for this is that the digital nature of the compensation and the voltage level resolution are dependent on the resolution of the digital to analog converter.

FIG. 10A illustrates a comparison of an adjustment of the V_(CELSRC) relative to changing sensed temperature. In the figure, the reference temperature is 85° C., where no compensation is provided. In an embodiment where the V_(CELSRC) has a DAC resolution of 12.5 mV, the amount of temperature compensation is always a multiple of 12.5 mV. Thus, discrete jumps of 12.5 mv are observed at various temperatures. Other resolutions of DACs are possible and within the scope of the present technology.

FIG. 10B illustrates a situation where multiple read/verify/program/erase parameters may be adjusted based on a temperature change to provide read/verify/program/erase compensation. When multiple parameters are adjusted, there may exist temperatures when multiple parameters switch at exactly the same temperature; when this occurs, the apparent cell threshold voltage (Vt) compensation may be too large. In the example shown in FIG. 10B, the contributions from various temperature-compensated parameters—including the bit line clamp voltage V_(BLC), cell source voltage V_(CELSRC), WL voltage V_(CGRV) and the sense amplifier's sense time SEN—are illustrated relative to temperature. In this example, three of the four parameters illustrated increase from 21° C. to 22° C., leading to a large jump when all are combined.

In one prior art implementation, only a limited number of parameters are adjusted at any given change in the TEMPCODE. In such cases, the effect illustrated in FIG. 10B is reduced, but the effectiveness of temperature compensation may be reduced as well.

Each parameter which is subject to temperature compensation may be selected and enabled in the memory system. For each parameter, the required difference between a current sensed temperature and a previously applied or “historical” temperature, may be defined.

It should be recognized that although temperature changes may induce a temperature correction in memory system, even when the ambient temperature is stable, noise may be present in a memory systems' sensed temperature values, causing fluctuations on the order of, for example, 1° C. If the ambient temperature is near one of these critical temperatures (where multiple parameters may be changing), the temperature compensation noise can cause unneeded corrections.

Embodiments of the memory system utilize a TEMPCODE stabilization technique to improve the stability of temperature compensation based on the TEMPCODE measurement. As discussed herein, a smoothing function is applied to measured TEMPCODE values to calculate whether a new, measured TEMPCODE should be used to provide temperature compensation in the memory system.

FIG. 11 illustrates a method in accordance with such embodiments. The method of FIG. 11 may be performed for each read, program verify, program, or erase operation. At 1102, the ambient temperature is measured using the circuit of FIG. 9 , for example, and stored at 1104. One or more historical TEMPCODE values may be stored in the storage region 913. At 1106, one or more historical TEMPCODE values may be accessed. At 1108, the measured TEMPCODE and one or more historical TEMPCODE values are utilized to calculate a new TEMPCODE using a smoothing function. As discussed below, the smoothing function may be a digital filter, a hysteresis-inducing function or a combination of both. Examples of various smoothing functions are set forth below. In embodiments, the smoothing function may result in the measured TEMPCODE (from step 1102) being used as the new TEMPCODE, or in no-change to the existing stored TEMPCODE. At 1110, if after applying the smoothing function, the output of the calculation is that the existing TEMPCODE should not change, than the method proceeds to step 1112 and no temperature compensation occurs. However, if the TEMPCODE is changed, then at 1114 the new TEMPCODE is stored and at 1116, the new TEMPCODE is utilized for temperature compensation and one or more parameters is adjusted if temperature compensation is needed.

One form of smoothing function comprises a hysteresis inducing function which introduces hysteresis into application of the TEMPCODE to temperature compensation. In this function, the measured TEMPCODE is compared with a previously applied (historical) TEMPCODE and when the new TEMPCODE has changed sufficiently from the historical TEMPCODE, the new TEMPCODE is stored as the current TEMPCODE and used for temperature compensation. In one aspect, the hysteresis inducing function may take the form:

${y\lbrack n\rbrack} = \left\{ \begin{matrix} {y\left\lbrack {n - 1} \right\rbrack} & {{{if}{❘{{x\lbrack n\rbrack} - {y\left\lbrack {n - 1} \right\rbrack}}❘}} \leq t} \\ {x\lbrack n\rbrack} & {{{if}{❘{{x\lbrack n\rbrack} - {y\left\lbrack {n - 1} \right\rbrack}}❘}} > t} \end{matrix} \right.$

where x[n] is the new, measured TEMPCODE, y[n] is the current TEMPCODE to be applied, and y [n−1] was the historical TEMPCODE that was previously used.

In another embodiment, the hysteresis inducing function may be expanded by substituting |x[n]−y[n−1]|≤t and |[n]−y[n−2]|≤t for |x[n]−y[n−1]|≤t in the above equation. This embodiment of the hysteresis-inducing function changes the calculation of the new TEMPCODE to be of greater magnitude relative to the two previously applied historical TEMPCODE values.

A second form of smoothing function comprises a digital filtering function. In this embodiment, when a new TEMPCODE is measured, the new TEMPCODE is averaged with a historical TEMPCODE in a weighted calculation. This allows any noise in the measured TEMPCODE to be smoothed before applying a measured TEMPCODE as a current TEMPCODE. In one embodiment, a smoothing function for digital filtering may take the form:

y[n]=ax[n]+bx[n−1]

where

a+b=1

In other embodiments, the hysteresis-inducing function and digital filtering functions may be combined. In one embodiment, a combined smoothing function may be generalized as:

${y\lbrack n\rbrack} = \left\{ \begin{matrix} {{\sum_{k = 0}^{M}{a_{k}{x\left\lbrack {n - k} \right\rbrack}}} + {\sum_{k = 1}^{N}{b_{k}{y\left\lbrack {n - k} \right\rbrack}}}} & {{{if}{❘{{x\lbrack n\rbrack} - {y\left\lbrack {n - 1} \right\rbrack}}❘}} \leq t} \\ {otherwise} & {x\lbrack n\rbrack} \end{matrix} \right.$

where x includes the past M TEMPCODE acquisitions (including the current acquisition), and y includes the past N TEMPCODE applications.

The effectiveness of the TEMPCODE smoothing can be seen relative to FIGS. 12-14 . FIGS. 12A-14A illustrate three temperature profiles and are used to describe the effectiveness of various embodiments of the smoothing function. FIG. 12A illustrates a steady temperature change ramp, where the temperature smoothly increases from 15° C. to 40° C. FIG. 13A illustrates a stable temperature with added noise at a stable ambient temperature at 21° C. Gaussian noise (with σ=0.5° C.) is added on top of the stable temperature profile. FIG. 14A illustrates an ambient temperature profile with large discrete jumps.

FIG. 12B illustrates the effectiveness of each of the hysteresis-inducing function and the digital filtering functions described above as compared to a prior art temperature compensation design when the memory system is subject to a continuously ramped temperature profile.

In FIG. 12B, the “Ideal Vt” curve shows the amount of Vt compensation ideally needed, without the discrete jumps caused by digital temperature compensation but still subject to quantization from the digital-to-analog converters (for voltage-based parameters) or digital clock (for time-based parameters). The prior art compensation design shows the behavior of a prior art temperature compensation design without using a smoothing function and limiting Vt threshold parameter modification to one parameter. The variable y represents the TEMPCODE that is used by the chip for compensation, while x represents the TEMPCODE that was actually measured. In the prior art designs the measured TEMPCODE is directly applied such that y[n]=x[n].

The “hysteresis” plot illustrates the behavior if the TEMPCODE is updated only when it is more than a threshold t=4° C. away from the last applied TEMPCODE such that:

${y\lbrack n\rbrack} = \left\{ \begin{matrix} {y\left\lbrack {n - 1} \right\rbrack} & {{{if}{❘{{x\lbrack n\rbrack} - {y\left\lbrack {n - 1} \right\rbrack}}❘}} \leq {4{^\circ}{C.}}} \\ {x\lbrack n\rbrack} & {otherwise} \end{matrix} \right.$

The “weighted” plot applies a digital filtering where the last acquired TEMPCODE is weighted twice as much as the newly acquired TEMPCODE (i.e. a=1/3 and b=2/3):

y[n]=1/3x[n]+2/3x[n−1]

Then the result is rounded and applied. Both the digital filtering and hysteresis-inducing smoothing functions track the ideal Vt well. In general, all three methods behave similarly.

FIG. 13B illustrates the effectiveness of each of a prior art temperature compensation design, the hysteresis-inducing function and the digital filtering function when subjected to a stable temperature profile with noise. In this example the ambient temperature is held stable at 21° C., and then Gaussian noise (in this case with a of 0.5° C.) is added. The prior art design shows Vt jumps when the noise occurs which causes the TEMPCODE to shift by 1° C. high or low. As noted, this would result in drastic temperature compensation shifts in a relatively stable temperature profile. The embodiments of the hysteresis-inducing smoothing function and the digital filtering smoothing function hold the temperature compensation (based on the TEMPCODE) relatively steady under noisy conditions.

FIG. 14B illustrates the effectiveness of each of a prior art temperature compensation design, the hysteresis-inducing function and the digital filtering function described above when the memory system is subjected to a temperature profile which has relatively large magnitude temperature changes.

The hysteresis algorithm may not make a jump if the temperature shift is small (i.e. at t=15 and 20). But when the temperature jump is large (i.e. at t=40), it can immediately accommodate this. The digital filtering algorithm can generally track the jumps well though it requires some time to “catch” up after some slight delay (such as at t=40).

FIGS. 12C through 14C illustrate the effectiveness of a smoothing function combining a hysteresis-inducing function and a digital filtering function. From the foregoing FIGS. 12B-14B, it can be seen that the digital filtering smoothing function performs well to compensate for noise fluctuations and avoids large jumps in TEMPCODE values when the temperature is ramped.

In the embodiment illustrated in FIGS. 12C-14C, the smoothing function first applies a weighted average unless the current temperature is 4° C. or more away from the previous TEMPCODE that was applied, at which point a hysteresis-inducing function is applied:

${y\lbrack n\rbrack} = \left\{ \begin{matrix} {{\frac{1}{3}{x\lbrack n\rbrack}} + {\frac{2}{3}{x\left\lbrack {n - 1} \right\rbrack}}} & {{{if}{❘{{x\lbrack n\rbrack} - {y\left\lbrack {n - 1} \right\rbrack}}❘}} \leq {4{^\circ}{C.}}} \\ {x\lbrack n\rbrack} & {otherwise} \end{matrix} \right.$

This embodiment smooths out noise, and adapts to large changes in temperature that might be due to long idle periods. Additional refinements are possible, such as fine-tuning the hysteresis threshold, or enforcing extra acquisitions under certain circumstances.

FIGS. 12C through 14C illustrate that the ramped temperature profile, noisy temperature profile and large temperature change profiles are all tracked well by a smoothing function combining a hysteresis-inducing function and a digital filtering function.

Embodiments of the present technology include an apparatus. The apparatus includes a non-volatile memory system comprising a block comprising non-volatile memory cells and a control circuit in communication with the non-volatile memory cells. The control circuit is configured to sense a current temperature of the memory system and program data into non-volatile memory cells associated in the block, sense a current temperature of the memory system and read and verify data in the non-volatile memory cells by modifying one or more read/verify parameters based on a temperature compensation value. The control circuit is further configured to sense a current temperature of the memory system and erase data from the non-volatile memory cells. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program, or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based on a smoothing function which utilizes the current temperature value and the historical temperature value. The control circuit then modifies one or more read, verify, program, or erase parameters when the temperature compensation value is different from the historical temperature value.

Embodiments of the present technology include a method of operating a non-volatile memory system. The method comprises during a read, verify, program, or erase operation on data stored in non-volatile memory cells in a block in the non-volatile memory system, programming at least an applied temperature value into memory cells of the block, the applied temperature value comprising a historical temperature value. During a subsequent read, verify, program, or erase operation which uses one or more read, verify, program, or erase parameters to read, verify, program, or erase the data, respectively, the method includes measuring a current temperature of the non-volatile memory system. Next, the method includes determining a temperature compensation value by applying a smoothing function which selects the temperature compensation value from one of the current temperature value, the historical temperature value, and a calculated compensation temperature value, based on the current temperature value and the applied temperature value. When a difference between the temperature compensation value and the historical temperature value exceeds a threshold, the method includes raising or lowering a one or more parameters to perform the read, verify, program, or erase operation.

Embodiments of the technology include a non-volatile memory system comprising a block comprising non-volatile memory cells, and a control circuit in communication with the non-volatile memory cells. The control circuit includes means for sensing a current temperature of the memory system and means for accessing a historical temperature value stored in the memory system, the historical temperature value comprising at least a temperature at which a previous read, verify, program, or erase occurred. The control circuit further includes means for determining the temperature compensation value by applying a smoothing function which selects the temperature compensation value from either the historical temperature value or a current temperature value when a difference between the historical temperature value and the current temperature value is above a threshold, and means for selecting a calculated temperature compensation value, calculated based on the current temperature value and the historical temperature value, when the difference between the historical temperature value and the current temperature value is below the threshold. The control circuit further includes means for reading, verifying, programming, and erasing data in the non-volatile memory cells, including means for modifying one or more read/verify/program/erase parameters based on the temperature compensation value when the temperature compensation value is different from the historical temperature value.

Corresponding methods, systems and computer- or processor-readable storage devices which have executable code for performing the methods provided herein may also be provided.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. For example, examples in which memory cells are programmed based on threshold voltage can be modified to program memory cells that store information based on resistance. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto. 

We claim:
 1. An apparatus, comprising: a non-volatile memory system comprising a block comprising non-volatile memory cells; and a control circuit in communication with the non-volatile memory cells, the control circuit configured to: sense a current temperature of the memory system; program, verify, read or erase data in the non-volatile memory cells by modifying one or more program, verify, read or erase parameters, respectively, based on a temperature compensation value by: accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read or verify occurred; measuring a current temperature value; determining the temperature compensation value by applying a smoothing function, the smoothing function determining the temperature compensation value by: selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold; or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value; and modify the one or more program, verify, read or erase parameters when the temperature compensation value is different from the historical temperature value.
 2. The apparatus of claim 1 wherein the smoothing function comprises a hysteresis-inducing function which selects the historical temperature value as the temperature compensation value when the difference between the current temperature value and the historical temperature value is below or equal to the threshold and selects the current temperature as the temperature compensation value when the difference between the current temperature value and the historical temperature value is above the threshold.
 3. The apparatus of claim 1 wherein the smoothing function comprises a hysteresis-inducing function which selects the historical temperature value as the temperature compensation value when the difference between the current temperature value and at least two historical temperature values is below or equal to the threshold, and selects the current temperature as the temperature compensation value when the difference between the current temperature value and the historical temperature value above the threshold.
 4. The apparatus of claim 1 wherein the control circuit calculates the temperature compensation value based on a smoothing function which calculates a weighted average of the historical temperature value and the current temperature value.
 5. The apparatus of claim 4 wherein the weighted average provides a larger weight to the historical temperature value than current temperature value.
 6. The apparatus of claim 4 wherein the control circuit calculates the temperature compensation value based on a weighted average of a first plurality of historical temperature values and a second plurality of current temperature values.
 7. The apparatus of claim 1 wherein the determining selects the temperature compensation value from either the historical temperature value or a current temperature value when a difference between the historical temperature value and the current temperature value is greater a threshold and calculates the temperature compensation value when the difference between the historical temperature value and the current temperature value is less than or equal to the threshold.
 8. The apparatus of claim 7 wherein the control circuit calculates the temperature compensation value based on a smoothing function which calculates a weighted average of the historical temperature value and the current temperature value, with a greater weight provided to the historical value than the current temperature value.
 9. A method of operating a non-volatile memory system, the method comprising: during a read, verify, program, or erase operation of data stored or to be stored in non-volatile memory cells in a block in the non-volatile memory system, programming at least an applied temperature value into memory cells of the block, the applied temperature value comprising a historical temperature value; during a subsequent read, verify, program, or erase operation which uses one or more read, verify, program, or parameters to read, verify, program, or erase the data, respectively, measuring a current temperature of the non-volatile memory system; determining a temperature compensation value by applying a smoothing function which selects the temperature compensation value from one of the current temperature value, the historical temperature value, and a calculated compensation temperature value, based on the current temperature value and the applied temperature value; and when a difference between the temperature compensation value and the historical temperature value exceeds a threshold, raising or lowering one or more read, verify, program, or erase parameters to perform the read, verify, program, or erase operation.
 10. The method of claim 9 wherein the smoothing function includes a hysteresis-inducing function which causes selection the temperature compensation value from either the historical temperature value or a current temperature value when a difference between the historical temperature value and the current temperature value is greater a first threshold, and the determining calculates the calculated temperature compensation value when the difference between the historical temperature value and the current temperature value is less than or equal to the first threshold.
 11. The method of claim 10 wherein the hysteresis-inducing function causes selection of the historical temperature value as the temperature compensation value when the difference between the current temperature value and the historical temperature value is below or equal to a second threshold and causes selection of the current temperature as the temperature compensation value when the difference between current temperature value and the historical temperature value is above the second threshold.
 12. The method of claim 11 wherein the determining calculates the temperature compensation value based on a weighted average of the historical temperature value and the current temperature value.
 13. The method of claim 12 wherein the weighted average provides a larger weight to the historical temperature value than current temperature value.
 14. The method of claim 12 wherein the determining calculates the temperature compensation value based on a weighted average of a first plurality of historical temperature values and a second plurality of current temperature values.
 15. A non-volatile memory system, comprising: a block comprising non-volatile memory cells; and a control circuit in communication with the non-volatile memory cells, the control circuit comprising: means for sensing a current temperature of the memory system; means for accessing a historical temperature value stored in the memory system, the historical temperature value comprising at least a temperature at which a previous read, verify, program, or erase occurred; means for determining the temperature compensation value by applying a smoothing function which selects the temperature compensation value from either the historical temperature value or a current temperature value when a difference between the historical temperature value and the current temperature value is above a threshold, and selects a calculated temperature compensation value, calculated based on the current temperature value and the historical temperature value, when the difference between the historical temperature value and the current temperature value is below the threshold; and means for reading, verifying, programming, and erasing data in the non-volatile memory cells, including means for modifying one or more read, verify, program, or erase parameters based on the temperature compensation value when the temperature compensation value is different from the historical temperature value.
 16. The non-volatile memory system of claim 15 wherein means for determining utilizes the smoothing function includes a hysteresis-inducing function which selects the temperature compensation value from either the historical temperature value or a current temperature value when a difference between the historical temperature value and the current temperature value is greater a first threshold, and the means for determining calculates the calculated temperature compensation value when the difference between the historical temperature value and the current temperature value is less than or equal to the first threshold.
 17. The non-volatile memory system of claim 16 wherein the hysteresis-inducing function which selects the historical temperature value as the temperature compensation value when the difference between the current temperature value and the historical temperature value is below or equal to a second threshold and selects the current temperature as the temperature compensation value when the difference between current temperature value and the historical temperature value is above the second threshold.
 18. The non-volatile memory system of claim 15 wherein the means for determining calculates the temperature compensation value based on a weighted average of the historical temperature value and the current temperature value.
 19. The non-volatile memory system of claim 18 wherein the weighted average provides a larger weight to the historical temperature value than current temperature value.
 20. The non-volatile memory system of claim 15 wherein the means for determining calculates the temperature compensation value based on a weighted average of a first plurality of historical temperature values and a second plurality of current temperature values. 